1. Field of the Invention
The present invention relates to a semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode.
2. Description of the Related Art
Several elements (transistors) forming a semiconductor device are mutually isolated via an isolation region formed on a semiconductor substrate. These elements each have different characteristics required in accordance with their functions. Moreover, the dimension of element region and isolation region is different in accordance with the characteristics.
For example, a non-volatile semiconductor memory having a two-layer gate electrode comprising a floating gate electrode and a control gate electrode is given as one example. In order to obtain a mass storage capacity, a memory cell requires to micro-fabricate the foregoing element region and isolation region as much as possible. On the other hand, in a peripheral transistor forming a peripheral circuit for driving the memory cell, the allowable dimension of the element region and isolation region is determined in accordance with required electric characteristics. For example, a high-voltage driving transistor is formed of an element region larger than the memory cell and an isolation region to prevent a leak current.
The following technique is employed to form the preceding memory cell and peripheral circuit. According to the technique, an isolation trench is formed, and thereafter, a semiconductor substrate sidewall functioning as an element region is oxidized. Etching damages caused in a semiconductor substrate are repaired when the isolation trench is formed, thereby preventing a junction leak current of impurities formed on the element region. The technique will be described below with reference to the drawings giving a NAND non-volatile memory device as one example.
FIG. 1A is a cross-sectional view showing a memory cell in the channel width direction. FIG. 1B is a cross-sectional view showing a peripheral transistor in the channel width direction.
The NAND non-volatile memory device is formed according to the following manufacturing method. Impurity ions are implanted into a silicon substrate 101 to form well of memory cell, channel region 102a, well of peripheral transistor and channel region 102b, and thereafter, a gate insulating film 103 is formed. Then, a floating gate electrode of the memory cell and a first gate electrode layer consisting of polysilicon are formed on the gate insulating film 103. In this case, the first gate layer functions as a gate electrode of peripheral and select transistors. Thereafter, a mask material (not shown) used for forming an isolation region is formed on the gate insulating film 103. A resist film protecting the element region is patterned using a lithography process, and the foregoing mask material, first gate electrode layer, gate insulating film 103 and silicon substrate 101 are successively etched. Trenches, that is, an isolation region 107a of the memory cell and an isolation region 107b of the peripheral transistor are formed to isolate (partition) the element region 106a thereof and the element region 106b thereof from each other.
The surface of the silicon substrate is oxidized using thermal oxidization to form silicon oxide films 108a and 108b. In this case, the silicon oxide film 108a is formed on the trench surface of isolation regions 107a of the memory cell. The silicon oxide film 108b is formed on the trench surface of isolation regions 107b of the peripheral transistor. The thermal oxidization is carried out, and thereby, a sidewall of a gate electrode 104a of the memory cell is formed with a silicon oxide film 109a. Simultaneously, a sidewall of a gate electrode 104b of the peripheral transistor is formed with a silicon oxide film 109b. 
Thereafter, the trench functioning as the isolation region is formed with an isolation insulating film 110, and planarized using CMP to remove the mask material. The height of the isolation insulating film 110 of the memory cell is reduced using etching as the need arises to form an inter-gate insulating film 111.
A part of the inter-gate insulating film 111 is removed in the peripheral transistor and the select transistor. Thereafter, a control gate electrode 112a of the memory cell, that is, second gate electrode layer is formed. In this case, the second gate electrode layer comprises a stacked film of polysilicon and silicide. In the peripheral transistor and the select transistor, the foregoing first and second gate electrode layers are electrically connected. Then, the gate electrode is patterned using lithography technique, and second gate electrode, inter-gate insulating film and first second gate electrode are successively etched to form a gate electrode.
Thereafter, an interlayer insulating film 114 is formed, and then, source/drain diffusion layer, contact electrode 115 and interconnect 116 are formed using a generally known process. In the manner as described, memory cell and peripheral transistor are formed as shown in FIG. 1A and FIG. 1B.
Silicon oxide films 108a and 108b formed on each sidewall of element regions 106a and 106b are formed having a thickness of 4 nm using dry oxidization at temperature of 1035° C. FIG. 2A and FIG. 2B are each enlarged views showing element regions, gate insulating film and gate electrode in the foregoing formation.
The silicon oxide film 108b formed on the sidewall of the element region 106b has a thickness T′sb required for preventing a junction leak current of the peripheral transistor. Even if excessive oxidization is given to the memory cell, the silicon oxide film 108a formed on the sidewall of the element region 106a of the memory cell has the same thickness T′sa as T′sb. For this reason, if the scale-down of the memory cell advances, the width of the element region 106a becomes narrow more than the necessity in the memory cell. As a result, there is a problem that device characteristic is worsened.
Moreover, in oxidization of the sidewall of the element region, the sidewall of the first gate electrode layer is also oxidized. The first gate electrode is formed of polysilicon; for this reason, it is oxidized faster than the silicon substrate formed of single crystal silicon. As a result, the width of a channel region controlled by the gate electrode becomes smaller than that of the element region. The oxidized amount of the sidewall of the first gate electrode layer, that is, thickness T′ga and T′gb in the memory cell and the peripheral transistor are the same. Since the peripheral transistor has a large-width element region 106b, the sidewall of the first gate electrode layer has almost no influence by oxidization. However, the memory cell has a small-width element region 106a. For this reason, the sidewall of the first gate electrode layer is oxidized, and thereby, the width of an effective channel region is reduced. As a result, there is a problem that device characteristic is worsened.
In oxidization of each sidewall of the silicon substrate and the gate electrode using thermal oxidization, the oxidization rate of the polysilicon gate electrode is faster than that of the silicon substrate formed of single crystal silicon. For this reason, the gate electrode is oxidized more than the silicon substrate. As a result, the end of the gate electrode 104a of the memory cell is positioned inside from that of the element region 106a formed on the silicon substrate by L′a. Likewise, the end of the gate electrode 104b of the peripheral transistor is positioned inside from that of the element region 106b formed on the silicon substrate by L′b. In this case, the foregoing distances L′a and L′b have the same value.
In oxidization of the sidewall of the element region, an oxidizing agent diffuses in the gate insulating film. For this reason, oxidization is given to the gate insulating film from the lateral direction; as a result, a wedge-shaped oxide film is formed. The wedge-shaped oxide film is formed in the same manner in the memory cell and the peripheral transistor. More specifically, a horizontal distance B′sa of the formed wedge-shaped oxide film from the end of the element region 106a of the memory cell is given. A horizontal distance B′sb of the formed wedge-shaped oxide film from the end of the element region 106b of the peripheral transistor is given. In this case, the horizontal distance B′sa is the same as the horizontal distance B′sb. Likewise, a horizontal distance B′ga of the formed wedge-shaped oxide film from the end of the gate electrode 104a of the memory cell is given. A horizontal distance B′gb of the formed wedge-shaped oxide film from the end of the gate electrode 104b of the peripheral transistor is given. In this case, the horizontal distance B′ga is the same as the horizontal distance B′gb.
Moreover, an angle θ′sa of the wedge-shaped oxide film formed at the end of the element region 106a of the memory cell is given. An angle θ′sb of the wedge-shaped oxide film formed at the end of the element region 106b of the peripheral transistor is given. In this case, the angle θ′sa is the same as the angle θ′sb. Likewise, an angle θ′ga of the wedge-shaped oxide film formed at the end of the gate electrode 104a of the memory cell is given. An angle θ′gb of the wedge-shaped oxide film formed at the end of the gate electrode 104b of the peripheral transistor. In this case, the angle θ′ga is the same as the angle θ′gb. The peripheral transistor does not so receive an influence by the wedge-shaped oxide film because it has a large-width element region. On the contrary, the memory cell has a small-width element region; for this reason, the wedge-shaped oxide film is formed, thereby increasing an effective thickness of the gate insulating film. As a result, there is a problem that device characteristic is worsened.
In order to solve the foregoing problem, the isolation regions of the memory cell and the peripheral transistor are formed separately from each other. By doing so, oxidization to the sidewall of the element region is carried out separately. However, in this case, the formation of the isolation region must be carried out two times, and this is a factor of causing the following problem. In other words, an area of the boundary for separately forming the memory cell and the peripheral transistor increases, and the number of manufacturing processes increase; as a result, the manufacture cast increases.
JPN. PAT. APPLN. KOKAI Publication No. 2004-186185 discloses the following proposal. According to the proposal, polysilicon layer and silicon substrate are etched to form an isolation trench. Thereafter, each exposed surface of the silicon substrate and the polysilicon layer is formed with a silicon oxide film having a thickness of 5 nm using thermal oxidization. However, the foregoing proposal can not solve the problem that the device characteristic of the memory cell is worsened.